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Książka = Book ; KS/1/2003/T33R05P07
Instytut Badań Systemowych. Polska Akademia Nauk ; Systems Research Institute. Polish Academy of Sciences
[4], 325-336 stron ; 21 cm ; Bibliografia s. 336
In this paper, hardware implemented artificial neural networks (ANN's) capable of learning on silicon are considered. The ability to learn within a chip means that the network can fast adapt to varying conditions during the recall phase, i.e. can learn in operation. This is impossible in classical ANN's. Thinking about building such adaptive networks became realistic only recently due to advances in CMOS processes. An important and difficult task in hardware implementations of the ANN's is to find proper solutions for analog circuits that can play a role of basie network elements such as synapses, analog [ocal memories and activation Junction circuits. Concrete realizations of these circuits have been presented. The shown circuits were designed in the Institute of Telecommunication, ATR in Bydgoszcz, Poland. The performed experimental studies concern a prototype CMOS chip, fabricated by Nordic in the framework of EUROPRACTICE.
Licencja Creative Commons Uznanie autorstwa 4.0
Zasób chroniony prawem autorskim. [CC BY 4.0 Międzynarodowe] Korzystanie dozwolone zgodnie z licencją Creative Commons Uznanie autorstwa 4.0, której pełne postanowienia dostępne są pod adresem: ; -
Instytut Badań Systemowych Polskiej Akademii Nauk
Biblioteka Instytutu Badań Systemowych PAN
15 paź 2021
1 lut 2021
0
https://rcin.org.pl./publication/193216